The operational speed and performance of an SDRAM (synchronous dynamic random access memory) is better than that of a DRAM (dynamic random access memory) which operates asynchronously, when the SDRAM is operated in synchronization with an external system clock and there are frequent sequential data read/write operations.
The operational speed and performance of the SDRAM is further improved when both the rising and falling edges of the system clock is used in reading and writing data, i.e., the clock rate is effectively doubled. This type of memory device is referred to as a double data rate (DDR) SDRAM. In a DDR SDRAM, a data strobe signal, commonly referred to as “DQS”, is used in conjunction with the system clock to strobe and clock memory data.
The DDR SDRAM also utilizes a 4-bit prefetch data processing method. Usually in a write operation of 4-bit prefetch DDR SDRAM, input data, which are arranged in parallel, are input in synchronization with the data strobe signal DQS, and a write command is input in synchronization with an external clock signal. The data are finally stored in a memory cell array. The memory device is characterized by an input/output interface parameter tDQSS. The input/output interface parameter tDQSS occurs due to the difference of domains between the data strobe signal DQS domain and the external clock signal EXTCLK domain.
FIG. 1 is a schematic block diagram which illustrates a conventional memory system 10. The system 10 includes a memory controller 12 which provides data and control signals to and from a memory circuit 14, which can be an SDRAM circuit. The memory circuit 14 includes SDRAM storage 18 including SDRAM memory cells, a SDRAM data input circuit 100 which controls the writing of data to the SDRAM memory cells, and other circuitry 20 for carrying out the functions of the memory circuit 14.
The interface between the memory controller 12 and the memory circuit 14 carries address (ADDR) and data (DIN) signals. It also carries various control and timing signals which can include the data strobe signal DQS, the external clock signal EXTCLK and commands (CMDs), which can include a chip select signal (CSB), a row address strobe signal (RASB), a column address strobe signal (CASB), and a write enable signal (WEB).
FIG. 2 is a schematic block diagram of a portion of an SDRAM data input circuit 100 illustrated in FIG. 1. Referring to FIG. 2, SDRAM 100 receives the data strobe signal DQS and the external clock signal EXTCLK. Accordingly, the circuit 100 operates in both the DQS domain and the EXTCLK domain and includes circuitry to operate in the two different domains.
The data strobe signal DQS domain circuitry 101 includes a data input buffer 110 inputting the data DIN and outputting internal data input PDIN, a data strobe signal DQS input buffer 120 inputting the data strobe signal DQS and outputting an internal data strobe signal PDQS, an inverter 130 generating an inverted data strobe signal PDQSB, and a plurality of flip-flops.
The clock signal EXTCLK domain circuitry 103 includes a clock input buffer 170 inputting the external clock signal EXTCLK and outputting an internal clock signal PCLK, a plurality of command input buffers 180 inputting command signals such as the chip select signal CSB, row address strobe signal RASB, column address strobe signal CASB, and write enable signal WEB, a command decoder 190 inputting the buffered command signals and outputting an internal write signal WRITE, and an internal circuit block 192 inputting the internal clock signal PCLK. The internal write signal WRITE is input to the clock input buffer 170 and is used in generating the internal clock signal PCLK. Accordingly, the internal clock signal PCLK is in synchronization with the external clock signal EXTCLK. As a result, the internal clock signal PCLK carries information with regard to the timing of a write command.
The data input circuit 100 is shown as a serial-input/parallel-output circuit that operates with a 4-bit prefetch. That is, four bits of serial data are input from DIN through the data input buffer 110 and are output as a internal data PDIN(1-4) to the plurality of flip-flops, which in turn convert the four bits of serial data into four bits of parallel data synchronized with rising and falling edges of the inverted internal data strobe signal PDQSB. The four bits of parallel data are written into a memory array in response to a clock signal derived from a system clock. The system clock and the external clock signal EXTCLK are the same signals in this specification. The input data DIN is sequentially input and arranged in parallel on predetermined internal nodes which are referred to herein as a first group of data lines DF1, DS1, DF2, and DS2, having sequentially input data. The names of nodes may be used as those of signals applied to them.
FIG. 3 is a schematic diagram of a flip-flop circuit 150 shown in FIG. 2. The flip-flop circuit 150 latches the internal data input signal PDIN in response to a low level of PDQSB signal. FIG. 4 is a schematic diagram of another flip-flop circuit 160–163 in FIG. 2. The flip-flop 160–163 latches an input signal in response to a low level of the PDQSB signal and outputs the internally latched data in response to a high level of PDQSB. The output data of the flip-flops 160–163 is arranged in a 4-bit parallel configuration. The flip-flops 164–167 have the same structure as those shown in FIG. 4. The data loaded on the first group of data lines DF1, DS1, DF2, and DS2 are prefetched to the second set of data lines DI1, DI2, DI3, and DI4 through flip-flops 164–167 in response to the internal clock signal PCLK. That is, the data on the first group of data lines DF1, DS1, DF2 and DS2 are passed to the second set of data lines DI1, DI2, DI3 and DI4 on a low level of the PCLK signal. The second data lines DI1, DI2, DI3, and DI4 are processed in parallel fashion and written into the memory cell array.
In the SDRAM 100, the reference signal that arranges the 4-bit data on the first data lines is the data strobe signal DQS, and the reference signal that prefetchs data in parallel on the second data lines is the internal clock signal PCLK which includes the timing of the write command. That is, arranging the 4-bit data on the first data lines occurs in the data strobe signal DQS domain, and parallel prefetching the 4-bit data occurs in the external clock EXTCLK domain. Accordingly, the input/output interface parameter tDQSS is defined to characterize the difference in the domains.
FIGS. 5A and 5B contain timing diagrams showing the write operation of FIG. 2. Referring to FIGS. 5A and 5B, at a C2 clock cycle and C4 clock cycle first and second write commands WRITE1 and WRITE2 are input, respectively. The data strobe signal DQS is input from C3 clock cycle. The input data DIN D1 to D8 are input in synchronization with the rising and falling edges of data strobe signal DQS. The data D1 to D4 are serially input with the first write command WRITE1. The data D5 to D8 are serially input with the second write command WRITE2. At every rising edge of the inverted internal data strobe signal PDQSB, the data loaded are: unknown-unknown-D1-D2, D1-D2-D3-D4, D3-D4-D5-D6, D5-D6-D7-D8. Thereafter the first data lines DF1, DS1, DF2, and DS2 are loaded to the second data lines DI1, DI2, DI3, and DI4 in response to the internal clock signal PCLK.
FIGS. 5A and 5B illustrate two cases, i.e., Case I and Case II, respectively, with regard to the relative timing between the occurrence of the data strobe signal DQS and that of the external clock signal EXTCLK. FIGS. 5A and 5B also illustrate an ideal case for comparison purposes. The parameter tDQSS is illustrated in the diagrams as the time between the occurrence of a rising edge of the external clock signal EXTCLK with a write command and the occurrence of the first rising edge of the data strobe signal DQS. In the ideal case, the rising edge of the DQS signal occurs simultaneously with the rising edge of the EXTCLK signal at the beginning of the C3 clock cycle. The parameter tDQSSmin of Case I (FIG. 5A) illustrates a time interval or delayed DQS in which DQS occurs prior to the rising edge of EXTCLK at C3, and tDQSSmax of Case II (FIG. 5B) illustrates a time interval or delayed DQS in which DQS occurs after the rising edge of EXTCLK at C3.
Referring to Case II in FIG. 5B, as tDQSSmax increases, an internal tDQSSmax parameter decreases. Referring to Case I in FIG. 5A, as tDQSSmin decreases, an internal tDQSSmin decreases. The internal tDQSSmax and internal tDQSSmin parameters are measures of the internal timing margins, i.e., internal margin 1 (IM1) and internal margin 2 (IM2), respectively, of the PCLK signal in the memory write fetch window. If either of these timing margins of the internal clock signal PCLK is reduced, high frequency operation of the circuit can deteriorate. That is, under Case II, if the timing margin IM1 (internal tDQSSmax) is substantially reduced, set-up time requirements of the circuitry, e.g., the flip-flops 164–167, may be violated, resulting in failure of the circuit. On the other hand, under Case I, if the timing margin IM2 (internal tDQSSmin) is substantially reduced, hold time requirements of the circuitry, e.g., the flip-flops 164–167, may be violated, also resulting in failure of the circuit. Accordingly, as the frequency of operation of the circuit increases, these problems are exacerbated.
Here, to prefetch the data D1, D2, D3, and D4 on the first data lines DF1, DS1, DF2, and DS2, the internal clock signal PCLK has to be generated between the data starting timing point and data ending timing point. The greater the timing margins of the tDQSSmax and tDQSSmin parameters, the better the frequency characteristic of the memory device will be. However, the higher the operation frequency is, the worse the timing margins of the parameters tDQSSmax/min are. If the amount of data is large, the variation of process, voltage, and temperature (PVT) is greater and the timing margin of tDQSS is reduced. Also, because of these variations, the circuit is more difficult for engineers to design.
Thus, it would be desirable to have semiconductor devices without the input/output interface parameter tDQSS to allow a write operation to be performed reliably at a high frequency range.